# What happens in the code if the positive edge of the reset signal and the positive edge of the reset signal happen at the same time.

Experimental Work (student’s work starts here)

Run the code given in practice example 1 in the online simulator and insert a screenshot of the output. Make sure to change the name of the instructor with your own name. (15 points)

[Insert your screenshot here]

Answer the below questions for the Verilog code given in practice example 1. (20 points, 5 points each)

What is the initial value of the counter? Explain your answer.

In which numbering system does this counter count: decimal or binary? Explain your answer.

What is the maximal binary number that this counter can count?

What happens in the code if the positive edge of the reset signal and the positive edge of the reset signal happen at the same time.

Modify the code given in practice example 1 so that it counts up from the binary sequence 0000 up to 1110. This counter should count every negative edge of the clock signal. The resent happens for a negative edge of the reset signal too.
(25 points)

Insert the Verilog code of the counter module and comment it. (20 points)

// Insert the Verilog code here

Run the code in the online simulator and insert a screenshot of the output. Make sure to display your own name. (5 points)

Modify the code given in practice example 1 so that it counts down from the binary sequence 111 down to 010. This counter should count every negative edge of the clock signal. The counter should reset to 111 for every negative edge of the reset signal. Insert the Verilog code of the counter module and comment it.
(25points)

Insert the Verilog code of the counter module and comment it. (20 points)

// Insert the Verilog code here

Run the code in the online simulator and insert a screenshot of the output. Make sure to display your own name. (5 points)

Consider the below Verilog code for a Shift-Left/Shift-Right SIPO register. Comment the code in detail and explain how the shifting process happens by mentioning an example of your own. (15 points)
module shift_register (clk, serial_in, shift_request, parallel_out);
input clk,serial_in,shift_request;
output [7:0] parallel_out;
reg [7:0] tmp;

always @(posedge clk)
begin
if (shift_request==1’b0)
begin
tmp = {tmp[6:0], serial_in};
end
else
begin
tmp = {serial_in, tmp[6:0]};
end
end
assign parallel_out = tmp;

Explanation: